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19-3103; Rev 0; 12/07
Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
General Description
The MAX3886 2.488Gbps/1.244Gbps/622Mbps CDR with SerDes (serializer/deserializer) is designed specifically for low-cost optical network terminal (ONT) applications in Gigabit passive optical network (GPON) and broadband passive optical network (BPON) fiber-tothe-home (FTTH) systems. It provides G.984- and G.983-compliant clock and data recovery (CDR) for the continuous downstream data signal, with an integrated 4-bit SerDes that has LVDS parallel interfaces and CML serial interfaces. The SerDes uses the recovered downstream clock for upstream serialization (loopback clock), providing optimum PON operation. The CDR frequency reference can be provided by a low-cost 19.44MHz SMD-type crystal or external LVCMOS source, and excellent jitter tolerance supports applications requiring FEC. An integrated burst-enable signal path also simplifies highperformance upstream burst timing. This 3.3V IC is housed in a 8mm x 8mm, 56-lead thin QFN package and operates from -40C to +85C.
Features
2.488Gbps, 1.244Gbps, and 622Mbps Clock and Data Recovery Meets G.984 and G.983 Jitter Requirements 4-Bit Serializer and 4-Bit Deserializer with Loop-Timed Serialization CML Serial I/O, LVDS Parallel I/O Integrated Reference Oscillator Uses 19.44MHz SMD Crystal Integrated Upstream Burst-Enable Signal Path
MAX3886
Ordering Information
PART MAX3886ETN+ TEMP RANGE -40C to +85C PINPACKAGE 56 TQFN (8mm x 8mm) PKG CODE T5688-2
+Denotes a lead-free package.
Applications
BPON/GPON Optical Network Terminal (ONT)
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V +3.3V
0.27F VCC RFCK1 19.4400MHz MAX3747/ 2.488G MAX3748 LIM AMP 1310nm MAX3643/ MAX3656 LD DRIVER RFCK2 SDI CFIL VCC MVCO MDDR MSYM MAC IC +3.3V VOICE SLIC
MAX3886
GPON CDR/SERDES PCLK (311MHz) PDATA (622Mbps) PDATA (311Mbps) PCLK (311MHz) BURST ENABLE DATA 10/100 ETHERNET
1490nm PON BiDi TRIPLEXER
PCKO PDO[3:0] PDI[3:0] 1.244G SDO PCKI BENO BENI GND LOCK FRST FERR
1550nm MAX3654 VIDEO TIA GPON OPTICAL NETWORK TERMINAL (ONT) 870MHz VIDEO
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC).................................-0.3V to +4.0V CML Input Voltage Range (SDI)...............-0.3V to (VCC + 0.3V) CML Output Current (SDO, BENO)...............................22mA LVDS Input Voltage Range (PCKI, PDI[3:0], BENI)......................-0.3V to (VCC + 0.3V) LVDS Output Voltage Range (RCKO, PDO[3:0], PCKO) ................-0.3V to (VCC + 0.3V) LVCMOS Input Voltage Range (MSYM, MDDR, FRST)............................-0.3V to (VCC + 0.3V) Three-State Input Voltage Range (MVCO)...................................................-0.3V to (VCC + 0.3V) LVCMOS Output Voltage Range (LOCK, FERR) ........................................-0.3V to (VCC + 0.3V) Voltage Range at CFIL, RFCK1, RFCK2, TP1, TP2, TP3, TP4 ...................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 56-Pin TQFN (derate 47.6mW/C above 70C)..........3808mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER Operating Temperature Power-Supply Voltage Downstream/Upstream Data Rates Reference Frequency Crystal Accuracy Crystal ESR Crystal Drive Crystal Load Capacitance Reference Clock Input Duty Cycle On-chip parallel capacitance When driven by an LVCMOS clock source 40 18 60 Internal or external oscillator Includes aging, temperature, and other contributors Fundamental type, AT-strip cut 10 SYMBOL TA VCC CONDITIONS MIN -40 3.0 See Table 2 19.4400 250 60 100 W pF % TYP MAX +85 3.6 UNITS C V Gbps MHz ppm
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA= +25C, unless otherwise noted. LVDS outputs terminated 100 differential, CML inputs terminated 100 differential, CML outputs terminated 100 differential.) (Note 1)
PARAMETER Supply Current SYMBOL ICC MVCO = 1 Serial Input Data Rate CDR CID Immunity CDR Sinusoidal Jitter Tolerance SDI to SDO Jitter Transfer f > fC Rate MVCO = open MVCO = 0 BER BER 10 -10 (Note 2) 10 -10 (Note 3) 0.3 CONDITIONS MIN TYP 240 2488.32 1244.16 622.08 > 100 0.7 0.1 Bits UI P-P dB Mbps MAX 310 UNITS mA
CDR/DESERIALIZER SPECIFICATIONS
(Notes 4, 5)
2
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA= +25C, unless otherwise noted. LVDS outputs terminated 100 differential, CML inputs terminated 100 differential, CML outputs terminated 100 differential.) (Note 1)
PARAMETER SDI to SDO Jitter Transfer Bandwidth Parallel Clock Output Random Jitter Parallel-Output Clock to Data Time Parallel Clock and Data-Output Rise/Fall Time Parallel-Clock Output Duty Cycle Parallel-Clock Output Frequency Parallel-Data Output Channel-to-Channel Skew CDR Acquisition Time (After Startup) Reference-Output Clock Frequency SERIALIZER SPECIFICATIONS Parallel-Input Clock Frequency Serial-Output Data Rate Parallel-Data Input-Setup Time Parallel-Data Input-Hold Time Serial-Data Output Rise/Fall Time Serial-Data Output Random Jitter Serial-Data Output Deterministic Jitter Burst Enable to Serial Data MSB Time Minimum Pulse Width of FIFO Reset Tolerated Drift Between PCKI and PCKO After FIFO Reset I/O SPECIFICATIONS CML Differential Input Voltage CML Input Common-Mode Range VIN 200 VCC 1.49 VCC 1.32 1600 VCC VIN/4 mVP-P V tB-MSB t SU tHD tr, t f Figure 1 Figure 1 20% to 80% (Notes 5, 6) (Notes 2, 5) Figure 2 UI is PCKO period UI is PCKO period -50 4 1 170 300 160 4 47 +50 See Table 2 See Table 2 MHz Mbps ps ps ps mUIRMS mUI P-P ps UI UI 2 See Table 2 tCK-Q tr, t f SYMBOL (Notes 3, 4) (Note 6) Figure 1 20% to 80% 45 See Table 2 100 -80 < 0.5 +80 300 55 CONDITIONS MIN TYP MAX fC UNITS MHz mUIRMS ps ps % MHz ps ms MHz
MAX3886
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA= +25C, unless otherwise noted. LVDS outputs terminated 100 differential, CML inputs terminated 100 differential, CML outputs terminated 100 differential.) (Note 1)
PARAMETER CML Differential Output CML Differential Output Resistance LVDS Input Voltage Range LVDS Differential Input Range LVDS Differential Input Resistance LVDS Output Voltage High LVDS Output Voltage Low LVDS Output Differential Voltage LVDS Output Offset Voltage LVDS Output Change in VOD LVDS Output Change in VOS LVDS Differential Output Resistance LVCMOS Input Voltage Low LVCMOS Input Voltage High LVCMOS Input Current Three-State Input Current LVCMOS Output Voltage Low LVCMOS Output Voltage High VOL VOH VIL VIH VIH = VCC or VIL = ground MVCO input, VIH = VCC or VIL = ground I OL = 100A I OH = -100A 2.0 -10 -50 VCC 0.2 +10 +50 0.2 VOD VOS | V OD | | V OS | Figure 3 VOS = (VOUT+ + VOUT-)/2, Figure 3 Between "0" and "1" Between "0" and "1" 80 100 925 250 1125 400 1275 25 25 140 0.8 V V A A V V (Note 5) SYMBOL CONDITIONS MIN 640 80 0 100 80 100 TYP 800 100 MAX 1000 120 2400 600 120 1475 mV mV mV mV mV mV mV mV UNITS mVP-P
Note 1: With a 19.4400MHz SMD AT-strip crystal at RFCK1 and RFCK2. Note 2: Pattern is 16 x 27 - 1 PRBS, 100 CIDs, 16 x 27 - 1 PRBS inverted, 100 CIDs inverted. Note 3: For 622Mbps operation, fC = 500kHz. For 1.244Gbps operation, fC = 1MHz. For 2.488Gbps operation, fC = 2MHz. Note 4: Jitter transfer from SDI to SDO, with parallel side looped back. Defined as: jitter on upstream signal UI downstream bit rate x Jitter transfer = upstream bit rate jitter on downstream signal UI Note 5: Guaranteed by design and characterization. Note 6: For 2.488Gbps operation, measurement bandwidth = 8kHz to 20MHz. For 1.244Gbps operation, measurement bandwidth = 4kHz to 10MHz. For 622Mbps operation, measurement bandwidth = 2kHz to 5MHz. For 155Mbps operation, measurement bandwidth = 0.5kHz to 1.3MHz.
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
1UI SDO PDO_ PDI1 PDI0 PDI3 PDI2 PDI1
PCKO (MDDR = 0)
BENO tB-MSB MIN tB-MSB MAX
PCKO (MDDR = 1) tCK-Q MIN tCK-Q MAX
Figure 2. Burst-Enable Timing
1UI
PDI_
PCKI tSU tHD
Figure 1. Parallel Interface Timing Diagrams
LVDS
RL = 100
V
VOD
VOUTSINGLE- ENDED OUTPUT VOUT+ VOD VOS
+VOD DIFFERENTIAL OUTPUT 0V -VOD VOD(P-P) = VOUT+ - VOUT-
Figure 3. Definition of LVDS Output Levels
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
1.244Gbps SERIAL DATA OUTPUT (MVCO = 1, MSYM = 0)
MAX3886 toc01
622Mbps PARALLEL DATA AND CLOCK OUTPUT (MVCO = 1, MDDR = 0)
MAX3886 toc02
622Mbps PARALLEL DATA AND CLOCK OUTPUT (MVCO = 1, MDDR = 1)
MAX3886 toc03
100mV/div
200mV/div
200mV/div
120ps/div
500ps/div
500ps/div
2.488Gbps JITTER TOLERANCE
MAX3886 toc04
1.244Gbps JITTER TOLERANCE
MAX3886 toc05
622Mbps JITTER TOLERANCE
SINUSOIDAL JITTER TOLERANCE (UIP-P) TOLERANCE EXCEEDS TEST EQUIPMENT GENERATION LIMIT 10
MAX3886 toc06 MAX3886 toc09
100 SINUSOIDAL JITTER TOLERANCE (UIP-P) TOLERANCE EXCEEDS TEST EQUIPMENT GENERATION LIMIT 10
100 SINUSOIDAL JITTER TOLERANCE (UIP-P) TOLERANCE EXCEEDS TEST EQUIPMENT GENERATION LIMIT 10
100
1
1
1
0.1
G.984 MASK
0.1 G.984 MASK 0.01
0.1
G.983 G.984 MASK
0.01 10k 100k 1M 10M JITTER FREQUENCY (Hz)
0.01 10k 100k 1M 10M 10k 100k 1M 10M JITTER FREQUENCY (Hz) JITTER FREQUENCY (Hz)
SDI TO SDO JITTER TRANSFER (SDI = 2.488Gbps)
MAX3886 toc07
SDI TO SDO JITTER TRANSFER (SDI = 1.244Gbps)
0 -1 JITTER TRANSFER (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 G.984 MASK
MAX3886 toc08
SDI TO SDO JITTER TRANSFER (SDI = 622Mbps)
1 0 -1 JITTER TRANSFER (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 G.983 G.984 MASK
1 0 -1 JITTER TRANSFER (dB) -2 -3 -4 -5 -6 -7 -8 -9 -10 1k 10k 100k 1M G.984 MASK
1
10M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
JITTER FREQUENCY (Hz)
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
PARALLEL CLOCK OUTPUT RANDOM JITTER vs. TEMPERATURE
MAX3886 toc10
MAX3886
SDO RANDOM JITTER vs. TEMPERATURE (SYMMETRIC, MSYM = 1)
MAX3886 toc11
SDO RANDOM JITTER vs. TEMPERATURE (ASYMMETRIC, MSYM = 0)
1.8 RANDOM JITTER (mUIRMS) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 SDO = 2.488Gbps SDI = 1.244Gbps BW = 4kHz TO 10MHz 8kHz 20MHz SDI ==1.244Gbps SDO 622Mbps BW = 4kHz TO 10MHz BW = 2kHz TO 5MHz SDO = 622Gbps SDI 155Mbps BW = = 2kHz TO 5MHz BW 0.5kHz 1.3MHz
MAX3886 toc12
1.0 0.9 RANDOM JITTER (mUIRMS) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -15 10 35 60 SDI = 1.244Gbps BW = 4kHz TO 10MHz SDI = 622Mbps 622Gbps BW = 2kHz TO 5MHz SDI = 2.488Gbps BW = 8kHz TO 20MHz
4.0 3.5 RANDOM JITTER (mUIRMS) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 -15 10 35 60 SDO = 622Gbps SDI 622Mbps BW = 2kHz TO 5MHz SDO = 2.488Gbps SDI = 2.488Gbps BW = 8kHz TO 20MHz SDO = 1.244Gbps SDI = 1.244Gbps BW = 4kHz TO 10MHz
2.0
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
Pin Description
PIN 1, 14, 15, 29, 42, 43, 56 2 3, 6, 12, 28, 46, 53 4 5 7 8 9 10 11 13 16 17 18 19 20 21 22 NAME GND TP1 VCC SDI+ SDIBENOBENO+ TP2 SDOSDO+ TP3 PCKI+ PCKIPDI3+ PDI3PDI2+ PDI2PDI1+ Supply Ground Test Pin, Reserved. Connect to GND for normal operation. +3.3V Supply Voltage Positive Serial Data Input, CML or LVPECL Negative Serial Data Input, CML or LVPECL Negative Burst-Enable Output, CML Positive Burst-Enable Output, CML Test Pin, Reserved. Connect to VCC for normal operation. Negative Serial Data Output, CML Positive Serial Data Output, CML Test Pin, Reserved. Connect to GND for normal operation. Positive Parallel Clock Input, LVDS Negative Parallel Clock Input, LVDS Positive Parallel Data Input 3, LVDS, MSB (First Serial Bit Out) Negative Parallel Data Input 3, LVDS, MSB (First Serial Bit Out) Positive Parallel Data Input 2, LVDS Negative Parallel Data Input 2, LVDS Positive Parallel Data Input 1, LVDS FUNCTION
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
Pin Description (continued)
PIN 23 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 44 45 47 48 49 50 51 52 54 55 -- NAME PDI1PDI0+ PDI0BENI+ BENIRCKO+ RCKOPDO3+ PDO3PDO2+ PDO2PDO1+ PDO1PDO0+ PDO0PCKO+ PCKOFERR FRST RFCK2 RFCK1 MDDR MSYM MVCO LOCK CFIL TP4 EP Negative Parallel Data Input 1, LVDS Positive Parallel Data Input 0, LVDS, LSB (Last Serial Bit Out) Negative Parallel Data Input 0, LVDS, LSB (Last Serial Bit Out) Positive Burst Enable Input, LVDS Negative Burst Enable Input, LVDS Positive Parallel Rate Reference Clock Output, LVDS Negative Parallel Rate Reference Clock Output, LVDS Positive Parallel Data Output 3, LVDS, MSB (First Serial Bit In) Negative Parallel Data Output 3, LVDS, MSB (First Serial Bit In) Positive Parallel Data Output 2, LVDS Negative Parallel Data Output 2, LVDS Positive Parallel Data Output 1, LVDS Negative Parallel Data Output 1, LVDS Positive Parallel Data Output 0, LVDS, LSB (Last Serial Bit In) Negative Parallel Data Output 0, LVDS, LSB (Last Serial Bit In) Positive Parallel Clock Output, LVDS; Rate/4 or Rate/8, depending on value of MDDR pin. See Figure 1 for timing diagram. Negative Parallel Clock Output, LVDS; Rate/4 or Rate/8, depending on value of MDDR pin. See Figure 1 for timing diagram. FIFO Error Output, LVCMOS. A high output indicates when the FIFO read and write clocks attempt to access the same register. Normally connected to MAC IC. FIFO Reset Input, LVCMOS. A high input resets the FIFO. Normally connected to MAC IC. Reference Clock Crystal Input. A 19.4400MHz crystal must be connected between RFCK1 and RFCK2; or a 19.4400MHz LVCMOS clock source (capable of driving up to 10pF load) can be connected through a 10pF 10% series capacitor to RFCK1, RFCK2 unconnected. Reference Clock Crystal Input. See Pin 47. Dual Data Rate Select Input, LVCMOS. A high input selects dual data rate (DDR) parallel clock output. See Figure 1 for timing diagram. Symmetric Select Input, LVCMOS. A high input selects symmetric operation, a low input selects asymmetric operation. See Table 2. VCO Rate Select Input, Three-State. See Table 2. PLL Lock Detector Output, LVCMOS. A high output indicates the PLL is in lock, this output can chatter when no valid input signal is present. PLL Filter Capacitor Connection. Connect a 0.27F ceramic capacitor (10%, 10V, X7R-type) between pin 54 and pin 53. Test Pin, Reserved. Connect to VCC for normal operation. Exposed Paddle. Connect to thermal and electrical ground. FUNCTION
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
Detailed Description
The MAX3886 CDR/SerDes provides 2.488Gbps/ 1.244Gbps/622Mbps clock and data recovery, plus 1:4 deserializer for continuous downstream data and 1:4 serializer for burst upstream data (Figure 4). Specifically designed for GPON and BPON ONT applications, the serializer uses the recovered downstream clock to serialize the upstream serial data (loop-timed serialization). The upstream rate can be configured to be either equal to the downstream rate (symmetric operation) or a submultiple of the downstream rate (asymmetric operation). A low-cost 19.4400MHz SMDtype crystal or external LVCMOS source serves as the CDR frequency reference, providing robust frequency acquisition and lock detection. A parallel rate reference clock output, derived from the recovered downstream signal, is provided for use by the MAC layer IC, and an integrated FIFO is provided to deal with phase variation between the serializer and MAC layer IC. Once the FIFO has been initialized, the serializer tolerates up to one parallel UI phase difference between the read and write clocks. The FIFO circuitry includes an error output that indicates when the FIFO attempts to read and write from the same location. An integrated burst-enable signal path also includes the FIFO to simplify upstream burst timing. The deserializer parallel output clock can optionally be configured for dual data rate (DDR) operation. The high-speed CML-format serial-data interfaces are compatible with Maxim burst-mode laser drivers and both CML and LVPECL limiting amplifiers. The parallel data interfaces are LVDS format for compatibility with FPGAs or ASICs. 2.488Gbps). An external filter capacitor, connected between CFIL and VCC sets the damping factor of the PLL. All jitter specifications are based on an external 0.27F capacitor. Modifying the value of CFIL changes jitter peaking, acquisition time, and loop stability but not loop bandwidth.
MAX3886
PLL Reference Clock Oscillator
An integrated oscillator provides a reference clock signal for robust CDR acquisition and lock detection. This oscillator requires a 19.4400MHz crystal connected between RFCK1 and RFCK2, or an external LVCMOS 19.4400MHz clock source can be used. See the Applications Information section for important information about crystal selection and how to connect an external clock source.
Deserializer and Parallel Output
The downstream data is deserialized, producing four parallel LVDS outputs, PDO[3:0]. The first serial data bit received on the SDI input is the most significant bit (MSB), which is routed to the parallel output PDO3. The LVDS parallel output clock, PCKO, can be configured for either full rate or half rate operation, as shown in the timing diagrams of Figure 1. The PCKO rate is controlled using the LVCMOS MDDR input. Set the MDDR pin to logic high to clock out parallel data on each edge of the PCKO clock.
Parallel Input, FIFO, and Serializer
Parallel data presented at the four LVDS data inputs PDI[3:0] is latched into the input register using the LVDS parallel input clock PCKI and clocked out of the ONT SerDes using the recovered serial clock. The parallel data bit PDI3 is the MSB and the first bit out of the serial SDO output. For GPON and BPON ONT applications, the clock multiplier unit (CMU) frequency synthesizer normally incorporated in SONET serializers is eliminated, improving PON performance. Asymmetric operation is configured using the LVCMOS MSYM input (see Table 2). The parallel clock is also output on the LVDS RCKO pins for use, if needed, by the MAC layer. The serializer's 4-bit-long FIFO accommodates phase variation between RCKO and PCKI. PCKI provides the FIFO write clock and the internal RCKO is the read clock (loading the 4:1 serializer); this arrangement allows the phase relationship between these two clocks to vary 1UI. In the event that valid read and write clocks attempt to access the same FIFO address, this error condition is indicated on the LVCMOS FERR output. To initiate the FIFO or clear an error condition, the LVCMOS FRST input must be asserted high for at least 4UI while valid clocks are present.
Serial Input Clock/Data Recovery
Clock and data recovery is provided by a phase-locked loop (PLL) with selectable 2.488GHz/1.244GHz/ 622MHz operation. The operating frequency is controlled by the three-state MVCO input. A phase detector and filter generate error voltage proportional to the phase difference between the internal VCO and the input data, and feedback in the PLL drives the error voltage to zero, aligning the recovered clock to the center of the input data for retiming. A frequency detector assists the PLL to "pull in" to the serial data and generates the lock indicator signal on the LOCK pin. When no valid input signal is present, the LOCK output can oscillate (chatter) as the PLL hunts for the input signal. The PLL VCO and integrated loop filter implement a second-order transfer function, with loop bandwidth dependent on the VCO rate selected (e.g., 1.5MHz for
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
CFIL
PDO3+ D Q LVDS PDO3SDI+ CML SDILOCK CMOS FREQ DETECT CLK/4 DIV 2 MVCO CMOS 0 1 0 DIV 2, DIV 4 CMOS MDDR 1 LVDS PCKOCDR PLL PD LPF VCO CLK Q LVDS PDO2PDO1+ Q LVDS PDO1RFCK1 OSC RFCK2 PDO0+ Q LVDS PDO0PCKO+ PDO2+
4-BIT SERIAL TO PARALLEL
DIV 4
CMOS
MSYM
RCKO+ LVDS RCKOCLK RD WR CLK LVDS
PCKI+ PCKIPDI3+ D LVDS PDI3PDI2+ D LVDS PDI2D Q D 4-BIT PARALLEL TO SERIAL D 5 x 4 FIFO PDI1+
SDO+ CML SDOQ
CLK
REGISTER
LVDS PDI1PDI0+ LVDS PDI0BENI+
BENO+ CML BENOQ
CLK D LVDS
BENICMOS FERR
MAX3886
CMOS
FRST
Figure 4. Functional Diagram
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
Burst-Enable Signal Processing
To minimize PON overhead, it is important that the laser driver burst-enable (BEN) signal correspond accurately with the beginning of the serial data burst. This is supported in the MAX3886 by the BENI LVDS input and associated signal path. The LVDS burst-enable signal from the MAC layer IC is passed through the same FIFO as the parallel data and output on the BENO CML output, which ensures that the laser driver's burst enable matches the beginning of the associated serial MSB. If FRST or FERR are high, the BENO output is forced low to prevent the laser driver from transmitting erroneous data. The parallel data setup and hold timing requirements also apply to the burst-enable signal. At power-up, the CDR takes approximately 50ms (if valid NRZ data is present) for initial acquisition while the internal reference oscillator, the PLL, and the frequency detector reach their operating conditions. During this startup period, the LOCK status output may provide false indication of a lock condition. Once the PLL and frequency detector are initialized, the nominal time for reacquisition of an NRZ input is 2ms. When valid NRZ input data is not present, the lock detector may produce a chattering LOCK indicator output while the PLL searches for the input frequency. If needed, an external digital filter can be used to mask this chattering.
MAX3886
Lock Detector Output
The lock detector operates by comparing a divideddown version of the VCO output to the reference clock. The LOCK output pin indicates lock (high) when the frequency difference between the reference clock and the CDR VCO is less than 250ppm, within the "pullin" range of the PLL. The LOCK output indicates out-of-lock (low) when the frequency difference between the reference clock and the CDR VCO becomes more than 500ppm. When valid input data is present, this provides a stable lock indication.
Table 1. Lock Detector Output
CDR INPUT Valid NRZ data No CDR input LOCK OUTPUT 1 0/1 (chatter)
Control Input Summary
Table 2 summarizes the clock and data rates as controlled by MVCO, MSYM, and MDDR.
Table 2. Clock and Data Rate Controls
Rx MVCO 0 0 0 0 Open Open Open Open 1 1 1 1 MSYM 0 0 1 1 0 0 1 1 0 0 1 1 MDDR 0 1 0 1 0 1 0 1 0 1 0 1 SDI RATE (Mbps) 622 622 622 622 1244 1244 1244 1244 2488 2488 2488 2488 PDO RATE (Mbps) 155 155 155 155 311 311 311 311 622 622 622 622 PCKO (MHz) 155 78 155 78 311 155 311 155 622 311 622 311 SDO RATE (Mbps) 155 155 622 622 622 622 1244 1244 1244 1244 2488 2488 PDI RATE (Mbps) 39 39 155 155 155 155 311 311 311 311 622 622 Tx PCKI (MHz) 39 39 155 155 155 155 311 311 311 311 622 622 RCKO (MHz) 39 39 155 155 155 155 311 311 311 311 622 622
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
Applications Information
Interfacing to the CDR/SerDes
The MAX3886 has CML, LVDS, and LVCMOS inputs and outputs. The high-speed CML (LVPECL-compatible) inputs, SDI, are biased to VCC - 1.3V with an onchip high-impedance network (Figure 5). Figures 6 and 7 provide examples of DC-coupled and AC-coupled termination networks that can be used to connect the limiting amplifier outputs (CML or LVPECL) to the SDI inputs. The two high-speed CML outputs, SDO and BENO, have internal 50 back terminations to VCC (Figure 8) and should be terminated with 50 to VCC or 100 differential at the laser driver inputs (Figure 9). The burst SDO and BENO outputs must be DC-coupled to the laser driver for proper operation. SDO can be AC-coupled if a continuous serial signal is provided between bursts (with gating provided by the laser driver BEN input). The LVDS outputs (PDO[3:0], PCKO, RCKO) require 100 differential termination for proper operation. The LVDS inputs (PDI[3:0], PCKI) are internally terminated with 100 differential resistance, eliminating the need for external termination when connected to an LVDS output (Figure 10). Equivalent circuits for the three-state input (MVCO), LVCMOS inputs (MSYM, MDDR, FRST), and LVCMOS
VCC 16k 5k SDI+ VCC VCC
VCC 5k SDI-
24k
MAX3886
Figure 5. CML (LVPECL-Compatible) Input
outputs (LOCK, FERR) are given in Figure 11, Figure 12, and Figure 13. For more information on interfacing to Maxim's high-speed I/O circuits, refer to Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
DC-COUPLED LIMITING AMPLIFIER Z0 = 50 CML Z0 = 50 100 SDISDI+
MAX3886
AC-COUPLED LIMITING AMPLIFIER Z0 = 50 CML 0.1F Z0 = 50 SDI100 0.1F SDI+
MAX3886
Figure 6. Interface to Limiting Amplifier (CML Outputs)
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
VCC DC-COUPLED LIMITING AMPLIFIER Z0 = 50 LVPECL Z0 = 50 82 82 SDI130 130 SDI+
MAX3886
AC-COUPLED LIMITING AMPLIFIER 0.1F Z0 = 50 LVPECL 0.1F Z0 = 50 143 143 SDI100 SDI+
MAX3886
Figure 7. Interface to Limiting Amplifier (LVPECL Outputs)
VCC
MAX3886
50
50 SDO+/BENO+ SDO-/BENO-
Figure 8. CML Outputs
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
SDO+ CML SDO-
Z0 = 50 100 Z0 = 50
IN+
IN-
MAX3886
CDR/SerDes BENO+ CML BENOZ0 = 50 Z0 = 50 100 BEN-
MAX3656/MAX3643
BURST-MODE LASER DRIVER BEN+
Figure 9. Interface to Laser Driver
MAC IC
MAX3886
Z0 = 50 LVDS 100 Z0 = 50 100 LVDS
Z0 = 50 LVDS 100 Z0 = 50 100 LVDS
Figure 10. LVDS Interface
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
FIFO Control Signals
VCC VCC P MVCO N
MAX3886
MAX3886
A valid input at FRST is required to initialize the FIFO after the relationship between PCKO or RCKO and PCKI has stabilized prior to operating the serializer, or after the FERR output has indicated that the FIFO has overflowed or underflowed due to the phase difference between PCKO or RCKO and PCKI exceeding its capacity. The MAC IC provides the control signal for FRST. FERR should not be directly connected to FRST. If the PCKI signal is interrupted between bursts, the FIFO must be reset before the beginning of each burst while valid clocks are present. If a continuous PCKI signal is provided between bursts, the FIFO maintains the correct FIFO counter values as long as the phase relationship does not change.
Figure 11. Three-State Input (MVCO)
Reference Clock Oscillator
The integrated reference oscillator requires a parallel resonant 19.4400MHz AT-strip cut crystal connected between pins RFCK1 and RFCK2. It has 18pF nominal (15pF to 21pF) of on-chip crystal load capacitance; any frequency error due to mismatch to the rated crystal load capacitance must be included in the budget for the difference between reference clock frequency and input data rate. Take care that the wiring capacitances at the nodes RFCK1 and RFCK2 are controlled (typically no more than 2pF) to ensure proper operation. To drive the reference clock with an external 19.4400MHz LVCMOS clock source, connect it to RFCK1 through a 10pF 10% series capacitor and leave RFCK2 open. The LVCMOS clock source must be capable of driving a 10pF load. To ensure proper acquisition, the maximum difference between the downstream data rate (divided down to 19.4400MHz) and 19.4400MHz clock should be 500ppm, including 57ppm required by the CDR itself. Table 3 shows a typical budget.
VCC
VCC P
MSYM MDDR FRST N
MAX3886
Figure 12. LVCMOS Inputs
VCC P
VCC
Table 3. Typical Frequency Budget
DESCRIPTION
LOCK FERR
f (ppm) 50 63 75 100 50 57 Total 395
NOTES G.983, G.984 e.g., 21ppm/pF from 18pF
Downstream Data Rate Crystal Load Capacitance Crystal Tolerance Crystal Temperature Stability Crystal Aging CDR Operation
N
MAX3886
Figure 13. LVCMOS Outputs
Total is less than 500ppm
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15
Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
MAX3886
Power Supply and Ground Connection
The MAX3886 has six VCC connection pads, and installation of a bypass capacitor at each VCC pad is recommended. All six VCC connections should be driven from the same source to eliminate the possibility of independent power-supply sequencing. Pin 53 provides current directly to the internal VCO stage; excessive supply noise at this node can result in increased jitter.
The 56-pin TQFN package features an exposed pad (EP) that provides a low resistance thermal path for heat removal from the IC and must be connected to the circuit board ground plane for proper operation. The EP also provides essential electrical ground connectivity.
Pin Configuration
TOP VIEW
PCKO+ RCKO+ PDO0+ PDO1+ PDO2+ PDO3+ PCKORCKOPDO0PDO1PDO2PDO3GND GND 28 VCC 27 BENI26 BENI+ 25 PDI024 PDI0+ 23 PDI122 PDI1+ 21 PDI220 PDI2+ 19 PDI318 PDI3+ 17 PCKIEP* 16 PCKI+ 15 GND 1 GND 2 TP1 3 VCC 4 SDI+ 5 SDI6 VCC 7 BENO8 BENO+ 9 TP2 10 11 12 13 14 SDO+ SDOTP3 GND VCC
42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND 43 FERR 44 FRST 45 VCC 46 RFCK2 47 RFCK1 48 MDDR 49 MSYM 50 MVCO 51 LOCK 52 VCC 53 CFIL 54 TP4 55 GND 56
MAX3886
+
THIN QFN (8mm x 8mm x 0.8mm)
* THE EXPOSED PAD OF THE THIN QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
16
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Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications
Chip Information
TRANSISTOR COUNT: 10,684 PROCESS: SiGe BiCMOS
Package Information
(For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE TYPE 56 Thin QFN DOCUMENT NO. 21-0135
MAX3886
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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